Analog IC Engineer
At GN-Hearing, we are working on our next generation chipset for use in our hearing instruments and other GN products. We are looking for an Analog IC Engineer, who can join the team around one of our DSP IC’s and contribute to its design and verification.
We have multiple IC projects running in our IC Team, both in mature CMOS nodes and in advanced nodes, where there will be room for development of your skills within many areas of analog and mixed mode IC design.
You will join a diverse and skilled team of + 30 analog, digital and physical IC designers, working right at the heart of GN-Hearing.
Maturing our mixed mode verification flow, we are working in a combined framework that allows for mixed mode verification of both analog top and digital top IC’s, interfacing to the digital and physical design workflows.
Ownership of the blocks you are responsible for, from system design to block specification, test specification, design, layout and verification. Block examples are LDO’s, ADC’s, Oscillators, Test muxes, I/O cells.
Study and understand the IC design, both from a top level and from a block level perspective. Network with the project team across analog, digital and physical IC design. As well as with neighboring teams working with electronics integration, Firmware, Systems Engineering and Radio systems.
Write and maintain Python modules and drivers, for our test framework.
Execute manual and automated parts of our test campaign, together with the rest of the project team. Analyse and document your results and present these to the team.
B.Sc. or M.Sc. in integrated analog electronics with some experience, working in CMOS. We use Cadence front-end EDA tools, and a mix of back-end and simulation tools from Cadence, Mentor and Synopsys.
Structured and analytical team player.
Experience with integrated analog circuit design in CMOS, i.e. band gap references, power on reset circuitry, opamps, comparators, LDO’s, I/O cells, etc.
Some experience with, or wish to learn, scripting in Python. We are currently converting our lab verification test flow from TCL to Object Oriented Python, relying on Pandas for data analysis, and Git for revision control of the code base.
Some experience with, or wish to learn, setting up mixed mode test benches, both in GUI mode and batch mode. We rely on a mix of simulators, such as Incisive, Xcelium and Symphony. Our digital blocks are described in VHDL, Verilog and SystemVerilog.
2023.02.01 or sooner.
Contact Kristian Lyngshede Lund, Manager, Analog IC, email@example.com
Please apply by using the apply button and following our process in our recruitment system, Workday.
We look forward to hearing from you.
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